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4-130 fast and ls ttl data synchronous presettable binary counter the mc74f161a and mc74f163a are high-speed synchronous modu - lo-16 binary counters. they are synchronously presettable for application in programmable dividers and have two types of count enable inputs plus a t er- minal count output for versatility in forming synchronous multistage counters. the mc74f161a has an asynchronous master reset input that overrides all other inputs and forces the outputs low . the mc74f163a has a synchro - nous reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. ? synchronous counting and loading ? high-speed synchronous expansion ? typical count frequency of 120 mhz connection diagram

function table sr pe cet cep action on the rising clock edge ( ) l x x x reset (clear) h l x x load (p n o q n ) h h h h count (increment) h h l x no change (hold) h h x l no change (hold) h = high v oltage level; l = low v oltage level; x = don't care state diagram
logic symbol
mc74f161a mc74f163a synchronous presettable binary counter fast ? shottky ttl j suffix ceramic case 620-09 n suffix plastic case 648-08 16 1 16 1 ordering information mc74fxxxaj ceramic mc74fxxxan plastic mc74fxxxad soic 16 1 d suffix soic case 751b-03

4-131 fast and ls ttl data mc74f161a ? mc74f163a note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. logic diagram

functional description the mc74f161a and mc74f163a count in modulo-16 binary sequence. from state 15 (hhhh) they increment to state 0 (llll). the clock inputs of all flip-flops are driven in parallel through a clock buf fer . thus all changes of the q out - puts (except due to master reset of the mc74f161a) occur as a result of, and synchronous with, the low -to-high transi - tion of the cp input signal. the circuits have four fundamental modes of operation, in order of precedence: asynchronous re - set (mc74f161a), synchronous reset (mc74f163a), parallel load, count-up and hold. five control inputs ? master reset (mr , mc74f161a), synchronous reset (sr , mc74f163a), parallel enable (pe ), count enable parallel (cep) and count enable t rickle (cet) e determine the mode of operation, as shown in the function table. a low signal on mr overrides all other inputs and asynchronously forces all outputs low . a low signal on sr overrides counting and parallel loading and allows all outputs to go low on the next rising edge of cp. a low signal on pe overrides counting and allows infor - mation on the parallel data (p n ) inputs to be loaded into the flip-flops on the next rising edge of cp . with pe and mr (mc74f161a) or sr (mc74f163a) high, cep and cet per - mit counting when both are high. conversely , a low signal on either cep or cet inhibits counting. the mc74f161a and mc74f163a use d-type edge-trig - gered flip-flops and changing the sr , pe , cep, and cet in- puts when the cp is in either state does not cause errors, pro - vided that the recommended setup and hold times, with respect to the rising edge of cp, are observed.
4-132 fast and ls ttl data mc74f161a ? mc74f163a guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 74 4.5 5.0 5.5 v t a operating ambient temperature range 74 0 25 70 c i oh output current e high 74 1.0 ma i ol output current e low 74 20 ma dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 1.2 v v cc = min, i in = 18 ma v oh output high voltage 74 2.5 3.4 v i oh = 1.0 ma v cc = 4.50 v 74 2.7 3.4 v i oh = 1.0 ma v cc = 4.75 v v ol output low voltage 0.35 0.5 v i ol = 20 ma v cc = min i ih input high current 20 m a v cc = max, v in = 2.7 v 0.1 ma vcc = max, v in = 7.0 v i il input low current data, cep, clock pe , cet, sr 0.6 1.2 ma v cc = max, v in = 0.5 v i os output short circuit current (note 2) 60 150 ma v cc = max, v out = 0 v i cc power supply current 37 55 ma v cc = max notes: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. not more than one output should be shorted at a time, nor for more than 1 second. the t erminal count (tc) output is high when cet is high and the counter is in state 15. t o implement synchronous mul - tistage counters, the tc outputs can be used with the cep and cet inputs in two dif ferent ways. the tc output is subject to decoding spikes due to internal race conditions and is there - fore not recommended for use as a clock or asynchronous reset for flip-flops, counters, or registers. logic equations: count enable = cep ? cet ? pe tc = q 0 ? q 1 ? q 2 ? q 3 ? cet
4-133 fast and ls ttl data

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4-134 fast and ls ttl data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . literature distribution centers: usa: motorola literature distribution; p .o. box 20912; phoenix, arizona 85036. europe: motorola ltd.; european literature centre; 88 t anners drive, blakelands, milton keynes, mk14 5bp , england. jap an: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, t okyo 141, japan. asia p acific: motorola semiconductors h.k. ltd.; silicon harbour center , no. 2 dai king street, t ai po industrial estate, t ai po, n.t., hong kong. ?
4-135 fast and ls ttl data mc74f161a ? mc74f163a ac characteristcs 74f 74f t a = +25 c t a = 0 c to 70 c v cc = +5.0 v v cc = 5.0 v 10% c l = 50 pf c l = 50 pf symbol parameter min max min max unit f max maximum count frequency 100 90 mhz t plh propagation delay, count 3.5 6.0 3.5 7.0 t phl cp to q n (pe input high) 3.5 10 3.5 11 ns t plh propagation delay 3.5 7.0 3.5 9.5 t phl cp to q n (pe input low) 4.0 8.5 4.0 9.5 t plh propagation delay 5.0 14 5.0 15 ns t phl cp to tc 4.5 14 4.5 15 t plh propagation delay 2.5 7.5 2.5 8.5 ns t phl cet to tc 2.5 7.5 2.5 8.5 t phl propagation delay mr to q n (mc74f161a) 5.5 12 5.5 13 ns t phl propagation delay mr to tc (mc74f161a) 4.5 10.5 4.5 11.5 ns ac operating requirements 74f 74f t a = +25 c t a = 0 c to 70 c v cc = +5.0 v v cc = 5.0 v 10% c l = 50 pf c l = 50 pf symbol parameter min max min max unit t s (h) setup time, high or low 5.0 5.0 t s (l) p n to cp 5.0 5.0 ns t h (h) hold time, high or low 2.0 2.0 t h (l) p n to cp 2.0 2.0 t s (h) setup time, high or low 11 11.5 t s (l) pe or sr to cp 8.5 9.5 ns t h (h) hold time, high or low 2.0 2.0 t h (l) pe or sr to cp 0 0 t s (h) setup time, high or low 11 11.5 t s (l) cep or cet to cp 5.0 5.0 ns t h (h) hold time, high or low 0 0 t h (l) cep or cet to cp 0 0 t w (h) clock pulse width (load) 5.0 5.0 ns t w (l) high or low 5.0 5.0 t w (h) clock pulse width (count) 4.0 4.0 ns t w (l) high or low 6.0 7.0 t w (l) mr pulse width, low (mc74f161a) 5.0 5.0 ns t rec recovery time, mr to cp (mc74f161a) 6.0 6.0

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